[tt] Next Big Future - 2 new articles
Eugen Leitl
<eugen at leitl.org> on
Fri Sep 19 08:25:26 CEST 2008
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Subject: Next Big Future - 2 new articles
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"[2]Next Big Future" - 2 new articles
1. [3]IBM Develops Computational Scaling Solution for Next Generation
"22nm" Semiconductors
2. [4]SiCortex Introduces the World's Most Energy Efficient
High-Productivity Computers
3. [5]More Recent Articles
4. [6]Search Next Big Future
[7]IBM Develops Computational Scaling Solution for Next Generation "22nm"
Semiconductors
[8]IBM (NYSE: IBM) today announced the semiconductor industry's first
computationally based process for production of next generation 22nm
semiconductors. Known as Computational Scaling (CS) -- a process that
enables the production of complex, powerful and energy-efficient
semiconductors at 22nms and beyond -- this new initiative will feature
support from several of IBM's key partners initially including Mentor
Graphics and Toppan Printing.
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[15]Computational lithography was used at the 32 nanometer lithography
node.
Intel technologists have also been working with [16]computational
lithography which involves etching pixels with various shapes and
slopes on what appears to be a totally transparent, chromeless piece
of glass. When 193 nm light is projected, the pixelated mask creates
phase-shifted patterns that could extend immersion lithography to 22
nm.
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Introducing circuits at 22nm is a challenging milestone since current
lithography methods -- the process of designing photomasks to image
circuit patterns on silicon wafers in mass quantity -- are not
adequate for critical layers at 22nm due to fundamental physical
limitations. Computational Scaling overcomes these limitations by
using mathematical techniques to modify the shape of the masks and
characteristics of the illuminating source at each layer of an
integrated circuit.
The individual components of IBM's CS solution include:
Source Mask Optimization
IBM has partnered with Mentor Graphics on a new resolution enhancement
technique to enable cost-effective printing of two dimensional
patterns for the 22nm semiconductor technology generation. This new
technology, know as source mask optimization, will provide a means to
minimize the use of double patterning by employing highly customized
sources with optimized mask shapes.
"Our partnership with IBM will ensure production-ready technologies
are in place when they are needed for the 22nm node," said Joseph
Sawicki, vice president and general manager for the design-to-silicon
division at Mentor Graphics. "Because this next generation solution
will be built on the familiar Calibre platform, designers will see a
smooth transition path to 22nm, and will also enjoy added benefits in
managing turnaround time and the cost of computing."
Virtual Fabricator
Together with Rensselaer Polytechnic Institute and the State of New
York, IBM has made significant investments in the area of high
performance computing and remains devoted to the advancement of
semiconductor technology through the establishment of the
Computational Center for Nanotechnology Innovations (CCNI). CCNI
provides the unprecedented computational power to enable accurate
predictions of advanced manufacturing processes. When combined with
predictive models and TCAD, this platform will allow virtual
co-optimization of semiconductor unit processes and critical circuit
design elements to cut development learning cycles and improve
time-to-market for advanced semiconductor technology.
Design Technology Co-Optimization
Within semiconductor fabrication, design 'rules' are created as an
abstract representation of the information or model that describes the
technology being created. Often, these rules are only defined after an
exhaustive negotiation process between the technology and design team.
To improve the timeliness and certainty of this process, IBM's Design
Technology Co-optimization (DTCO) process helps integrate and automate
this complex procedure, cutting the time it takes to reach a clear and
stable set of rules for use by the circuit design teams.
Design Enablement Tools
As a result of using IBM's DTCO, a semiconductor modeling process will
have a new class of design rules that are simpler and more
prescriptive (what to do vs. what not to do). Working with engineering
design automation (EDA) suppliers, IBM will be providing new design
enablement solutions for a seamless transition.
Critical Dimension Variance Control
Working with leading equipment suppliers, IBM will play the role of
lead integrator of providing an adaptive control system to minimize
critical dimension variance. As a result production yield and circuit
parameters will be more stable reducing the cost of production.
Photomask Fabrication
To address the gap in raw optical resolution, aggressive resolution
enhancement techniques such as SMO drive unprecedented minimum feature
sizes on the photomask -- the opaque plate with holes or
transparencies that allow light to shine through in a defined guide
for casting the circuit patterns. IBM has partnered with Toppan to
ensure timely availability of masks with the required feature sizes.
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[34]SiCortex Introduces the World's Most Energy Efficient High-Productivity
Computers
[35]SiCortex, maker of energy-efficient high-productivity computing
(HPC) platforms, today announced that it has doubled the
price/performance metric of its entire product line. This breakthrough
is the result of increased processor speed, advancements to system
software and leading-edge compilers. SiCortex computers scale from 72
to 5,832 processors running Linux and other open-source codes, in
packages ranging from desk-side to departmental to the data center.
All are uniquely simple to deploy: unpack, plug in, turn on.
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SiCortex's breakthrough cost-per-teraflop sets a new standard for
delivered price/performance, in particular when considering the Total
Cost of Ownership (TCO) due to savings in power, cooling, staffing and
space. Compared to Intel x86-based cluster systems, SiCortex computers
deliver:
* Up to twice the delivered Results/$CapEx advantage
* Up to nine times the results-per-kilowatt advantage
* Up to three times results/$TCO advantage over a 3-year period
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The SiCortex 5832 is the first and only computer system to pack Top500
performance onto a single backplane. It offers 5832 1GFlops 64-bit
processors, each dissipating just 600 milliwatts of power. [43]The
SC5832 was a 5.8 teraflop system (Nov 2006) but with double the
performance it would be almost 12 teraflops.
Before doubling performance the systems had:
o The SC5832, which is a 5.8 Teraflop system with up to 8 Terabytes of
memory. The
SC5832 fits into a single cabinet and draws 18 KW of power.
o The SC1458, which is a 1458 Gigaflop system with up to 1.94
Terabytes of memory.
The SC1458 fits in a single cabinet and draws 4 KW of power
o The SC648, which is a 648 Gigaflop system with up to 864 Gigabytes
of memory.
A single SC648 system draws 2 KW of power.
o The SC072, which is a 72 GigaFlop system with 48 Gigabytes of
memory. The lowpower
desk-side cabinet uses less than 200 watts of power.
[44]SiCortex recently closed on a $37 million round of venture
funding.
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